Sound

Digital Delay For Application in Surround Sound

2.0 THEORY

The practical side of the project was divided up into 2 distinct parts; the digital and the analogue.

2.1 DIGITAL

The basic way in which information is directed into and out of the digital domain whilst creating the delay is as follows :

1) The RAM reads from the ADC.
2) The 14-bit counter then increments the address on the RAM.
3) The RAM writes to the DAC.

Steps 1 to 3 are then repeated.

This simple routine is the basis on which the whole conversion, delay and reconstruction process is carried out.

2.1.1 Conversion and RAM

SAMPLING
Sampling takes place at 64kHz for three reasons:
i) It obeys Shannon's theorem, which states that sampling must be carried out at a frequency of at least twice the highest frequency to be digitised (in this case 20kHz is the highest frequency).
ii) 64 kHz makes the variable time delay easier to produce when changing in one milli-second steps.
iii) The reconstruction filter used after the DAC will not need to have such a steep role-off rate.

QUANTISATION
Quantisation was chosen to be 16-bit for two specific reasons:
i) It gives good signal resolution with a high theoretical signal to noise ratio/dynamic range (96dB).
ii) 16-bit is used predominantly in audio, especially with CD and DAT. It is also possible to find both analogue to digital and digital to analogue converters which handle information in parallel form (handling data this way simplifies the circuitry).

The most important devices used in the project were the Analogue to Digital converter, and the Digital to Analogue converter, around which everything else is centred.

ANALOGUE TO DIGITAL CONVERTER (ADC)
The Burr-Brown ADS7805 is a 16-bit capacitor based successive approximation register. After much careful consideration it was chosen for the following reasons: i) It gave the digital data out in a single 16-bit parallel word. ii) It has the ability to be forced into a high impedance state at the digital outputs. This was essential because the RAM would be putting data onto the data bus at the same time as the ADC was acquiring a sample. This could result in a conflict within the ADC if it did not have the ability to go into high a impedance mode, possibly causing data corruption. iii) It was the cheapest device which also held true to the above requirements.
The ADC is controlled by two binary state control lines CS and R/C. By applying the correct logical combinations (refer to timing diagram, FIG 2.1, section (2.1.3). The ADC can be made to a) start a conversion, b) go into high a impedance state, or c) output the converted data.

DIGITAL TO ANALOGUE CONVERTER (DAC)
The Burr-Brown PCM54JP was chosen for the following reasons:
i) It accepts the digital data as a single 16-bit parallel word.
ii) It is specified particularly for digital audio applications.
iii) It accepts a number of different binary formats.
iv) It was the cheapest device which also held true to the above mentioned requirements.

The only disadvantage of the PCM54JP, is that it cannot latch the data on-board itself, and so external latches are required. This does not however present any real problems.

In order for the DAC to receive the correct binary format from the ADC, which outputs the data in two's complement, inverters were used and the DAC was configured in bipolar mode as complementary offset Binary.

RANDOM ACCESS MEMORY (RAM)
The NEC UPD43256A is an 8-bit, 32k byte static RAM. It was chosen simply because it was cheap. Two of these were used in total to make up the required 16-bit word. Because of the nature of the delay required, only 16k byte of each RAM was used. It is controlled by three control lines WE, OE and CS. CS was tied low and only WE and OE were used. The UPD43256A can be forced into a high impedance state, and this facility was used in this application to ensure that data was loaded into and out of the RAM correctly.

14-BIT UP COUNTER
The 14-bit counter was made up of FOUR cascaded synchronous MC14516B binary up/down counters configured in UP mode. The two most significant bits were not needed in this application and so were ignored. The essential requirement of these counters was that they could be reset to zero on the application of a pulse. Each counters was wired for synchronous clocking and resetting.

Refer to APPENDIX A for conversion circuit block diagram.

2.1.2 Control

VARIABLE DELAY
The variable delay setting is based upon the 14 address lines controlling the RAM via the 14-bit up counter. The total number of addressable locations in RAM becomes 2¹⁴ = 16384.
By obeying the three step routine outlined in section 2.1 DIGITAL, samples are constantly read from storage in the RAM to the DAC, before being overwritten by new data from the ADC.
At 64kHz one clock cycle takes 15.625 x 10^-6 seconds (t = 1/f), this gives a total possible time delay of (15.625 x 10^-6) x 16384 = 256 x 10^-3 seconds (256ms).
It is then a case of varying the number of cycles between the read to RAM and write to RAM in order to vary the time delay.

This variation in time delay is achieved by making use of the fact that the seventh bit, (A6), will only change every 2⁶ x 1/(64kHz) Seconds; i.e. 64 x 15.625x10^-6 = 1x10^-3 Seconds (1 ms). Therefore by using this and the remaining seven most significant bits (MSB's - eight in total), one milli-second step delay time increments can be achieved up to the maximum of 255 milli-seconds (254 milli-seconds in reality for reasons to be explained later).

TABLE 2.0 Relationship Between Time and MSB's

When the display is reading zero the signal passes through the processor effectively in real time. The 14-bit up counter reset line is held high, initiating a reset, i.e. all bits equal zero. The ADC still writes to the RAM, but the DAC calls the data from the RAM almost immediately. The through rate of the signal will not be instantaneous, but any delays which do occur will be negligible.

MAGNITUDE COMPARATOR
A separate output from the eight MSB's is taken to the input of an 8-bit magnitude comparator. Also going into the comparator is the output from a separate 8-bit up/down counter, and when the two eight bit words are equal a control line is flagged. This control line can then be used to reset the 14-bit counter when it corresponds to the stationary value designated by the 8-bit counter. This has the effect of limiting the number of memory locations which are read from and written to in RAM, and hence the time delay.

8-BIT UP/DOWN COUNTER
The value of the 8-bit counter is set by the use of a rotational incremental encoder situated on the front panel. By employing simple circuitry, it controls the 8-bit up/down counters up/down line, and clock. This control circuity also offers the same information to the decade/counter driver which displays the equivalent of the 8-bit counters binary number in decimal form as a four digit number.

DECADE/COUNTER DRIVER
The decade/counter driver used operates four common cathode, seven segment displays. The displays have a decimal point which is hard wired in place, so that the delay time is always shown in fractions of seconds. As an example F0₁₆ on the 8-bit up/down counter (241₁₀) which is the equivalent of 241 ms would be read from the display as 0.241.

In order to stop the decade/counter driver from incrementing beyond the maximum value of the 8-bit counter, which could theoretically display numbers up to 9.999, it needed to be reset before it clocked the number 0.256, as numbers beyond 0.255 would be invalid. Due to time constraints and the requirement to keep the circuity as basic as possible the problem was solved by the use of one chip, an eight input nand gate. This simply monitored the output of the 8-bit counter, such that when its maximum value was reached (255 = FF₁₆) it flagged a line which reset both the 8-bit up/down counter and the decade/counter driver.

This gave rise to two effects:
1) It shortened the maximum theoretical time delay possible by 1ms, i.e. offering 254 ms instead of 255 ms.
2) When the incremental encoder is turned beyond 0.254, the display goes back to 0.000, but if the user then attempts to go below zero, it simply sits at 0.000. In order to reach 0.254 the incremental encoder has to be turned all the way again.

The time delay is incremented by clockwise rotation of the incremental encoder, and decremented by anti-clockwise rotation.
A block diagram of the control circuit can be found in APPENDIX A.

2.1.3 Timing and Master Reset

TIMING
In order to operate the digital delay, six individual control lines were needed: CS and R/C for the ADC, WE and OE for the RAM, RESET for the 14-bit counter and LATCH ENABLE for the DAC latches.
By implementing very careful design the CS control line could be combined with the 14-bit counter RESET line, and R/C could be combined with the DAC LATCH ENABLE line. This meant that only FOUR separate control lines needed to be generated.

The entire timing arrangement of one COMPLETE CYCLE, i.e. acquiring a sample from the ADC, and outputting stored data from the DAC, was achieved by an absolute minimum of SIX events. This ensured that the MASTER CLOCK frequency was kept as low as possible.
This can be more easily understood and visualised by referring to FIG 2.1.

FIG 2.1 Timing Diagram

Acquiring a sample only takes place on one of the six timing events, (and is indicated by the negative going arrow on the CS line of the timing diagram). Hence a MASTER CLOCK was used to clock at six times the sampling rate, i.e. 6 x 64kHz = 384kHz.
The output of this clock was divided down using combinational logic, which consisted of an arrangement of three D-type flip-flops, two 2-input NOR gates and one 3-input NOR gate. The master clock signal was derived from a 555 timer I.C. configured in astable mode.

Derivations for the logic equations and block diagram of the circuit used can be found in APPENDIX B.

RESET
In order to ensure that all the counters (14-bit, 8-bit and the decade/counter driver) were synchronised on start up (as they would otherwise contain random information), a circuit was created to reset all these counters to zero on initial switch on. This was achieved by the use of a 555 timer I.C. configured in a monostable mode.

2.2 ANALOGUE

2.2.1 Input

The left and right input signal from the source first meet a trim-pot which offsets the differences which may occur between the two channels of the source. Next is an instrumentation amplifier which derives the difference between the left and the right signals. The instrumentation amplifier also sets the gain of the differential signal, which is controlled by an anti-log potentiometer situated on the front panel of the processor. After which the signal is DC blocked before undergoing filtering by a Butterworth fourth-order low-pass filter with a corner frequency of 20kHz (filter 1) [23], [24]. Refer to APPENDIX C.
The signal is also monitored by an overload detector (before filter 1) which illuminates an L.E.D. on the front panel if the signal exceeds ± 10 Volts. This ensures that no clipping and hence distortion of the signal occurs at the input to the ADC. After the filter the signal goes to the input of the ADC.
Also at the input stage is a separate summing amplifier which sums the left and right channel information producing a monaural signal which is terminated on the rear of the processor with phono sockets.

2.2.2 Output

From the output of the DAC the signal first meets an eighth-order elliptic filter (filter 2) which has the corner frequency set by a clock, the ratio of which is 100:1. Therefore for a cut-off frequency of 20kHz the clock was set to be at 2MHz.
After filter 2 a further filter is introduced (filter 3). This is to remove the clock frequency of 2MHz which will be modulated onto the signal. A simple Butterworth second-order filter with a cut-off frequency of 40kHz was chosen for two reasons:
i) The clock frequency is so high that a filter with a gradual roll-off will suffice.
ii) The corner frequency set at 40kHz will not interfere with the frequency and phase characteristics of filter 2 within the audio spectrum.

After filter 3 the signal meets a D.C. block before passing through a unity gain buffer. The buffer ensures isolation from the external world, and also stops the D.C. block characteristic being affected by the output voltage trim-pot. The output is then terminated on to two separate phono sockets.
N.B. The maximum theoretical r.m.s. output of a CD player is = 1.414 x 3V, hence the output trim-pots are set so the absolute maximum output at the monaural and surround outputs are 1.414 x 3V r.m.s.. The mono and surround outputs are in anti-phase with respect to the input. Hence the speakers for these outputs need simply to be wired in anti-phase with respect to the main left and right speakers.
Block diagrams of the circuits used can be found in APPENDIX A.

2.2.3 Power Supply

The power supply was a simple arrangement which provided 4 separate power rails; +5V, +12V, -12V and -5V. Step down from 240V was achieved by the use of a toroidal transformer rated at 240:(12 x 1.414).
Refer to APPENDIX A for the block diagram of the circuit used

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