 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Sound
Digital Delay For Application in Surround Sound
APPENDIX B
TIMING EQUATIONS AND CIRCUIT BLOCK DIAGRAM
Implementation of Timing Decode Logic Using D-Type Flip-Flops and NOR Gates
NEXT STATE EQUATIONS
State Diagram
|
Q2 |
Q1 |
Q0 |
Q2+ |
Q1+ |
Q0+ |
|
0 |
0 |
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
1 |
0 |
0 |
0 |
|
1 |
1 |
0 |
1 |
0 |
0 |
|
1 |
1 |
1 |
0 |
0 |
0 |
State Table
DECODE LOGIC EQUATIONS
|
Q2 |
Q1 |
Q0 |
CS/Counter |
R/C DAC |
WE |
OE |
|
0 |
0 |
0 |
0 |
0 |
1 |
0 |
|
0 |
0 |
1 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
1 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
1 |
1 |
1 |
|
1 |
1 |
0 |
0 |
1 |
0 |
1 |
|
1 |
0 |
0 |
0 |
1 |
1 |
1 |
|
1 |
0 |
1 |
1 |
1 |
1 |
1 |
|
1 |
1 |
1 |
0 |
1 |
1 |
1 |
Note: Although the last two states in the table were not used, the equations were derived anyway. This was so that if any glitches occurred in the circuit and these states appeared, the derived logic outputs would be equivalent to the last state conditions of the loop and hence re-correct the logical flow back to normal.
Methods for deriving logic equations can be found in references [25] & [26].
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
